To find out the parameters of JFETs, both n-channel and p-channel, the simple and inexpensive attachment to the voltmeter described below will help, which allows you to measure a zero-gate voltage drain current (IDSS) and a gate-to-source cutoff voltage (VGS(OFF)). Thus, using only this attachment with some kind of voltmeter, you can, for example, select JFETs with the best characteristics or select a pair of JFETs with the same parameters. In addition, the attachment allows you to check JFET for performance, to clear up the transconductance at the intended DC operating point, and for students and novice radio amateurs to examine the field effect transistor in order to better understand its principle of operation.
The schematic diagram of the attachment to the voltmeter for measuring the parameters of JFETs is shown in Fig.1. Its main feature is a stabilized drain-to-source voltage when measuring the zero-gate voltage drain current (IDSS) of JFET.
Such a parameter of JFET as a zero-gate voltage drain current (IDSS), by definition, should be measured at zero gate-to-source voltage (UGS=0V) and a fixed drain-to-source voltage (UDS=const). In practice, to measure the zero-gate voltage drain current (IDSS) of JFET, a milliammeter is included in its drain or source circuit. But this method of measurement does not correspond to the actual definition of JFET’s parameter “zero-gate voltage drain current (IDSS)”, since the intrinsic ohmic resistance of a real milliammeter is non-zero. When such a milliammeter is connected to the source circuit, as shown in Fig.2a, due to the current flowing through the milliammeter, a potential difference arises between the source and the gate of JFET, and therefore UGS voltage will no be zero. For example, the self-resistance of the DT9205A multimeter in the current measurement mode at the “20 mA” range is 10 ohms. A current of just 10 mA will create a voltage across it 10mA x 10ohms = 0,1V, which is already significant.
A less criticism is caused by the measurement circuit shown in Fig.2b, where the milliammeter is connected to the drain circuit of JFET. Here, the voltage drop across the milliammeter only leads to a change in the drain-to-source voltage. But this, in turn, also causes some change in the drain current, since the drain characteristics of JFETs, as a rule, is far from ideal, especially at drain-to-source voltages below 5V.
On the schematic diagram of the attachment-measuring static parameters of JFETs, shown in Fig.1, a stabilized supply voltage is supplied to the drain of the connected JFET (“+5V” for an n-channel transistor and “-5 V” for a p-channel – set by switch SA1) , and its source is connected to the “virtual ground” of the current-to-voltage converter on the operational amplifier D3:1. Fig.3 shows a simplified circuit for measuring the zero-gate voltage drain current (IDSS) of JFET, which explains the principle of stabilizing the drain-to-source voltage.
The operational amplifier with negative feedback seeks to set such a voltage at its output in order to maintain, if possible, a voltage at its inverting input that is practically equal to the voltage at the non-inverting input. And since the non-inverting input of the op-amp is connected to ground, the voltage at its inverting input will also be very close to the ground potential (zero), at least as long as the op-amp operates within its linear region. This point of the circuit with a stabilized zero potential, but not galvanically connected to ground, is also called “virtual ground”.
The schematic diagram in Fig.3 shows that the voltage at the inverting input of the operational amplifier will be zero when the current flowing through the resistor R8 is equal to the source current of JFET connected to the “virtual ground” (we neglect the very low input current of the operational amplifier). The voltage at the output will then be proportional to the value of this current, and the proportionality coefficient is set by the resistance of the resistor R8. The voltage between the source and drain of JFET remains constant and equal to the supply voltage applied to the drain (in this case +5V).
In order to measure the gate-to-source cutoff voltage (VGS(OFF)) of JFETs, to find the slope of their transfer characteristic, or simply to study their operation for educational purposes, it is necessary to be able to adjust the voltage at the gate of a JFET. The schematic diagram in Fig.4 explaines how the operational amplifier D3:2 with a rheostat R7 in feedback performs this function.
A constant current flows through the rheostat R7, and the value of this current is determined by the sum of the resistances of the resistors R2 and R5. The operational amplifier D3:2 with a rheostat R7 in the negative feedback circuit maintains such a voltage at its output that the potential of the “virtual ground” is equal to the ground potential (zero), then the output voltage will be directly proportional to the resistance of the rheostat R7.
The gate-to-source cutoff voltage (VGS(OFF)) of JFETs of various types varies over a fairly wide range. Therefore, in the schematic diagram shown in Fig.1, switching of the voltage regulation range at the gate is provided by the SA3 switch: in its upper position according to the schematic diagram, the maximum voltage value is set by the trimmer resistor R2, and in the lower position by the trimmer resistor R3.
The stabilization of Uds voltage and the forming of the control Ugs voltage described above made it possible to simplify switching between JFETs of two different types: with an n-channel and a p-channel. This function is performed by a single switch SA1. When it is set to the “n-channel” position, then a stabilized positive supply voltage of +5V is applied to the input of the regulator of Ugs voltage and the drain of JFET. In this case, a negative control voltage will be applied to the gate of JFET from the output of the regulator. When the switch SA1 is set to the “p-channel” position, then the input of the regulator of Ugs voltage and the drain of JFET are supplied with a stabilized negative supply voltage of -5V, and a positive control voltage will be applied to the gate of JFET from the output of the regulator.
The purpose of the other switches shown in the schematic diagram is as follows. SA2 turns off the device while connecting of JFET. When SA2 is on, the green LED VD4 is on for an n-channel JFET or the yellow VD5 for a p-channel one. Switch SA4 disables the gate of JFET from the regulator of Ugs voltage made on the operational amplifier D3:2 when measuring the zero-gate voltage drain current (IDSS). And finally, with the switch SA5, you can select the value measured by the voltmeter connected to the contacts XT4 and XT5: either the source current of JFET (lower position according to the schematic diagram) or the voltage at its gate (upper position according to the schematic diagram).
Capacitive load compensation circuits R9:C8 and R10:C7 prevent possible self-oscillation of operational amplifiers, instigated by connecting long wires to their output, with which the device is connected to a voltmeter.
Fig.5 shows the power supply schematic diagram of the attachment-measuring static parameters of JFETs. Two secondary windings of the mains transformer connected to AC-terminals of the bridge rectifier VD3, but the midpoint of these windings connected to ground. The effective AC-voltage at the terminals of the secondary winding, measured relative to the midpoint, must be within 7..11 V, since the supply voltage of the operational amplifier D3 does not stabilize.
The attachment-measuring parameters of JFETs, including power supply, is assembled on a double-sided printed circuit board with dimensions 62 x 66 mm. The tracing of conductors on the printed board is shown in Fig.6, and the placing of elements on it is shown in Fig.7. Chips D1 and D2 are low-power linear voltage regulators MC78L05ABP and MC79L05ABP, respectively, in a TO-92 package.
Fig.6. Tracing of conductors on the double-sided printed circuit board.
The D3 chip is a dual LM358P or LM2904P general purpose op amp in a DIP-8 package. Electrolytic capacitors C1 and C2 may be of smaller capacity, but for an operating voltage of at least 25V. When installing, you must not make a mistake with their polarity. When installing the diodes VD1 and VD2 you must not make a mistake with their polarity also: for the 1N4448 diodes shown in the wiring diagram, the cathode terminal is marked with a strip. LED VD4 – green L-934GD, and VD5 – yellow L-934YD manufactured by Kingbright or similar in color and size. Rectifier diode bridge VD3 type DF01M.
Fig.7. Placement of elements on both sides of the printed circuit board.
Setting up of the assembled attachment consists in setting the adjustment ranges of the voltage at the gate of JFET by the trimming resistors R2 and R3. The order is this:
Fig.8. Сontacts for connecting JFET.
The procedure for measuring the parameters of JFET is as follows. Before inserting JFET into the contacts “G”, “D” and “S” (gate, drain and source, respectively), you have to connect a voltmeter to the attachment and apply power, then by switch SA1 to set the channel type corresponding to your JFET (“n” or “p”), and to set the SA2 switch to the “OFF” position. When measuring the zero-gate voltage drain current (IDSS) of JFET, the SA4 switch must be set to the “GND” position, and the SA5 switch to the “IS” position. Then:
When measuring of the gate-to-source cutoff voltage (VGS(OFF)) of JFET, by switch SA3 you have to select the voltage adjustment range at its gate (“2V” or “8V”) corresponding to the type of connected JFET and bring the variable resistor R7 engine to the leftmost position according to the schematic diagram (counterclockwise until it stops). Then:
The measurement range of a zero-gate voltage drain current (IDSS) of JFETs is limited by the maximum output current of the operational amplifier D3, in this case it is something around 20 mA. In order, for example, to select a pair of JFETs of the same parameters, in which the zero-gate voltage drain current (IDSS) can exceed this value (the zero-gate voltage drain current (IDSS) of such JFET as J310 can reach up to 60 mA), it is necessary to measure not the zero-gate voltage drain current (IDSS) of such JFETs, but the drain current at one and the same voltage on the gate, for example, by switching the switch SA3 to the “2V” position and turning the gate voltage regulator R7 to the extreme position clockwise. The SA4 switch must be in the “Adj.” position.
Copyright © Sergii Zadorozhnyi, 2011
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